EP910IPC-12 vs EP910IPC-25 比較
詳細並排比較 EP910IPC-12 由 Altera 與 EP910IPC-25 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910IPC-12 | EP910IPC-25 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Classic EPLD | Classic EPLD (EP910 series) |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | 450 |
| Maximum Operating Frequency (fMAX) | 76.9 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 12 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Dedicated Inputs | 10 | 12 |
| I/O Pins | 24 | — |
| 封裝 | 40-pin PDIP | 40-pin PDIP (PDIP-40) |
| 安裝類型 | Through Hole | Through-Hole |
| Technology | CMOS EPLD (UV-erasable or OTP) | — |
| 工作溫度 | -40C to +85C (industrial) | 0C to +70C (commercial grade) |
| Programming Toolchain | MAX+PLUS II | — |
| Logic Capacity | Equivalent to ~24 PAL16V8s | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | — |
| Manufacturer | — | Altera (now Intel) |
| Architecture | — | PAL-type EPLD, CMOS, UV/OTP |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Frequency (fMAX) | — | 40 MHz |
| Bidirectional I/O Lines | — | 24 |
| Total Inputs (max) | — | 36 |
| Total Outputs (max) | — | 24 |
| Programming Method | — | EPROM cell (OTP / UV erasable) |
| Development Tool | — | MAX+PLUS II |