EP910LC-30Y vs EP910IPC-25 比較
詳細並排比較 EP910LC-30Y 由 Altera 與 EP910IPC-25 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LC-30Y | EP910IPC-25 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | Altera Classic EPLD | Classic EPLD (EP910 series) |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | 450 |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Counter Frequency (fMAX) | 100 MHz (family maximum) | — |
| 供應電壓 | 5 V (TTL-compatible) | — |
| Process Technology | CMOS, UV-erasable / OTP | — |
| 封裝 | PLCC-44 | 40-pin PDIP (PDIP-40) |
| 工作溫度 | Commercial 0C to +70C | 0C to +70C (commercial grade) |
| Speed/Power Grade | LC (low-power, 30ns) | — |
| Processing Flow | Y (extended reliability) | — |
| Logic Compatibility | 100% TTL emulation | — |
| 安裝類型 | Surface Mount (PLCC socket) | Through-Hole |
| RoHS 狀態 | [DATA_NEEDED: RoHS status not specified in retrieved data] | — |
| Manufacturer | — | Altera (now Intel) |
| Architecture | — | PAL-type EPLD, CMOS, UV/OTP |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Frequency (fMAX) | — | 40 MHz |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O Lines | — | 24 |
| Total Inputs (max) | — | 36 |
| Total Outputs (max) | — | 24 |
| Supply Voltage (VCC) | — | 5 V |
| Programming Method | — | EPROM cell (OTP / UV erasable) |
| Development Tool | — | MAX+PLUS II |