EP910LC30T vs EP910LC44-30T 比較

詳細並排比較 EP910LC30T 由 Intel 與 EP910LC44-30T 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Intel
EP910LC30T EP910LC30T - 24-Macrocell Classic EPLD, 30ns, PLCC-44 | Intel

EP910LC30T - 24-Macrocell Classic EPLD, 30ns, PLCC-44 | Intel

EP910LC30T ⚠ 最後購買機會

規格比較

參數 EP910LC30T EP910LC44-30T
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 最後購買 Obsolete
Device Family Altera Classic EPLD Classic EPLD
Logic Capacity 450 equivalent gates —
Macrocells 24 24
Propagation Delay 30 ns (tpd) —
Maximum Frequency 33.3 MHz —
供應電壓 5 V —
Process Technology CMOS (LC low-power variant) —
Programmable Elements UV-erasable EPROM —
封裝 44-pin PLCC (J-Lead), Tape and Reel PQCC-44 (Plastic Leaded Chip Carrier, J-bend)
工作溫度 [DATA_NEEDED: operating temperature range] —
安裝類型 Surface Mount Surface Mount
MSL 等級 [DATA_NEEDED: MSL level] —
RoHS 狀態 [DATA_NEEDED: RoHS status] —
Programming Interface Altera ByteBlaster-compatible —
Manufacturer Intel (formerly Altera); currently supplied by Rochester Electronics —
Logic Type — PAL-type CMOS EPLD (OT PLD)
Product Terms — 240
Propagation Delay (tPD) — 33 ns
Supply Voltage (VCC) — 4.75 V to 5.25 V (nominal 5 V)
Dedicated Inputs — 12
I/O Lines — 24 (bidirectional)
Total Inputs — 36
Total Outputs — 24
External Clock Inputs — 2
Programming Technology — CMOS, UV-erasable (windowed package in family)
Security Bit — Programmable (logic readback protection)
Operating Temperature Grade — Commercial
Terminal Form — J-BEND
Package Code — QCCJ

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