EP910LI-35 vs EP910LC-35 比較
詳細並排比較 EP910LI-35 由 Altera 與 EP910LC-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LI-35 | EP910LC-35 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | Altera Classic EPLD | Classic (EP910) |
| Device Series | EP910 | — |
| Usable Gates | 900 | 450 |
| Macrocells | 24 | 24 |
| Maximum User I/O Pins | 38 | — |
| Propagation Delay (t_PD) | 35 ns | — |
| Maximum Counter Frequency (f_CNT) | 76.9 MHz | — |
| 供應電壓 | 5 V (4.75 V to 5.25 V) | — |
| 工作溫度 | -40 °C to +85 °C (Industrial) | 0C to +70C (commercial) |
| 封裝 | 44-pin PLCC (J-lead) | PLCC-44 (J-lead, LC suffix) |
| Process Technology | CMOS EPROM | — |
| Programming Technology | EPROM (UV-erasable) | — |
| Erase/Program Cycles | ≥100 | — |
| 安裝類型 | Surface Mount | — |
| Lead Pitch | 1.27 mm | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Toggle Frequency | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Technology | — | CMOS EPROM |
| 腳位數 | — | 44 |
| Programmable Flip-Flops | — | Yes (per macrocell) |
| Output Enable Control | — | Per macrocell |
| Erasure Method | — | UV (windowed) or OTP (plastic) |
| RoHS 狀態 | — | Not applicable (legacy product) |