EP910LI-35BF vs EP910LI-30 比較
詳細並排比較 EP910LI-35BF 由 Altera 與 EP910LI-30 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP910LI-30 - 24-Macrocell EPLD, 30ns, PQCC44 | Rochester/Altera
EP910LI-30 Obsolete規格比較
| 參數 | EP910LI-35BF | EP910LI-30 |
|---|---|---|
| 品牌 | Altera | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD | — |
| Part Number Base | EP910 | — |
| Logic Density | 450 usable gates | — |
| Macrocells | 24 | 24 |
| Maximum Pin-to-Pin Delay (tpd) | 35 ns | — |
| Maximum Toggle Frequency (fmax) | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal) | 5 V ±5% (4.75 V to 5.25 V) |
| 封裝 | 44-pin PLCC (J-lead) | 44-pin PQCC / PLCC-44 (J-lead) |
| 工作溫度範圍 | Industrial (LI suffix) | — |
| Technology | CMOS, UV-erasable | — |
| Programming Method | EPROM/UV-erase programmer (Altera Classic algorithm) | Altera EPLD programming algorithm / MAX+PLUS II legacy support |
| Output Polarity Control | Programmable XOR per macrocell | — |
| Flip-Flop Type | Selectable D/T/JK/SR per macrocell | — |
| TTL Compatibility | 100% TTL emulation | — |
| Compliance / EOL Status | Obsolete - last-time buy exhausted; second-source via Rochester Electronics | — |
| Family | — | Altera Classic EPLD EP910 |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Equivalent Gates | — | 450 |
| Propagation Delay (tPD) | — | 30 ns |
| Supply Current (ICC) | — | [DATA_NEEDED: ICC standby/active] |
| 工作溫度 | — | -40C to +85C (Industrial) |
| Process Technology | — | CMOS EPROM, UV-erasable |
| 安裝類型 | — | Surface Mount (socket recommended for UV erasure) |
| Dedicated Inputs | — | 10 |
| I/O Pins | — | 22 |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS compliance not verified in scraped data] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Manufacturer (Original) | — | Altera (now Intel PSG) |
| Current Stocking Channel | — | Rochester Electronics (authorized aftermarket) |