EP910LI44-35 vs EP910LC44-40 比較
詳細並排比較 EP910LI44-35 由 Altera 與 EP910LC44-40 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LI44-35 | EP910LC44-40 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Device Family | Altera Classic EPLD | — |
| Series | EP910 | — |
| Architecture | PAL-type macrocell (EPLD) | — |
| Number of Macrocells | 24 | — |
| Number of External Clocks | 2 | — |
| 最大時脈頻率 | 37 MHz | — |
| Propagation Delay (tPD) | 35 ns | 40 ns |
| Process Technology | CMOS | — |
| 供應電壓 | [DATA_NEEDED: VCC range] | — |
| 腳位數 | 44 | — |
| Package Type | PLCC-44 (J-lead) | — |
| 安裝類型 | Surface Mount / Through-Hole Socket | Surface Mount |
| 工作溫度 | [DATA_NEEDED: temperature grade] | 0C to +70C (commercial) |
| Programmability | UV-erasable / one-time programmable | — |
| RoHS 狀態 | unknown | [DATA_NEEDED: RoHS compliance] |
| Logic Family | Classic EPLD | — |
| Family | — | Altera Classic EPLD |
| Macrocells | — | 24 |
| Product Terms (Total) | — | 240 |
| I/O Pins | — | 24 (bidirectional) |
| Dedicated Inputs | — | 12 |
| Total Inputs | — | 36 |
| Global Clock Inputs | — | 2 |
| Supply Voltage (VCC) | — | 5 V (nominal) |
| Technology | — | CMOS, UV-erasable EPROM |
| Logic Compatibility | — | TTL-compatible I/O |
| 封裝 | — | 44-pin PLCC (Plastic Leaded Chip Carrier) |
| Programming Method | — | JEDEC file via LP6/MP9 or compatible programmer |