EP910LI44 vs EP910LI-35 比較
詳細並排比較 EP910LI44 由 Altera 與 EP910LI-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LI44 | EP910LI-35 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | Classic EPLD | Altera Classic EPLD |
| Architecture | PAL-type, CMOS, One-Time-Programmable | — |
| Macrocells | 24 | 24 |
| Package Type | PLCC-44 (J-lead, surface mount) | — |
| Total Pins | 44 | — |
| Dedicated Inputs | 12 | — |
| Bidirectional I/O | 24 | — |
| Maximum Logic Inputs | 36 | — |
| Maximum Outputs | 24 | — |
| Flip-Flops | 24 | — |
| External Clocks | 2 | — |
| Maximum Propagation Delay | [DATA_NEEDED: tpd for unmarked speed grade; speed-grade suffix encodes value: -15 = 15 ns, -20 = 20 ns, -25 = 25 ns, -30 = 30 ns, -35 = 35 ns, -40 = 40 ns, -45 = 45 ns, -50 = 50 ns] | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (commercial), 4.5 V to 5.5 V (industrial) | — |
| Operating Temperature (L grade) | -40 °C to +85 °C (industrial) | — |
| Technology | CMOS | — |
| Programmability | UV-erasable (windowed) or OTP | — |
| RoHS 狀態 | non-compliant (original PLCC-44 lead finish) | — |
| 安裝類型 | Surface Mount (PLCC socket compatible) | Surface Mount |
| Programming Method | Altera Logic Programmer card / Data I/O / third-party EPROM programmers | — |
| Device Series | — | EP910 |
| Usable Gates | — | 900 |
| Maximum User I/O Pins | — | 38 |
| Propagation Delay (t_PD) | — | 35 ns |
| Maximum Counter Frequency (f_CNT) | — | 76.9 MHz |
| 供應電壓 | — | 5 V (4.75 V to 5.25 V) |
| 工作溫度 | — | -40 °C to +85 °C (Industrial) |
| 封裝 | — | 44-pin PLCC (J-lead) |
| Process Technology | — | CMOS EPROM |
| Programming Technology | — | EPROM (UV-erasable) |
| Erase/Program Cycles | — | ≥100 |
| Lead Pitch | — | 1.27 mm |