EP910PI-40 vs EP910PC-25 比較
詳細並排比較 EP910PI-40 由 Altera 與 EP910PC-25 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910PI-40 | EP910PC-25 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Device Family | Classic EPLD | — |
| Part Number | EP910PI-40 | — |
| Architecture | PAL-type macrocell, CMOS, UV-erasable | — |
| Number of Macrocells | 24 | — |
| Number of Dedicated Inputs | 12 | — |
| Number of I/O Lines | 24 | — |
| External Clock Inputs | 2 | — |
| 最大時脈頻率 | 25 MHz | — |
| Propagation Delay (tPD) | 43 ns | — |
| Speed Grade | -40 (43 ns) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V +/- 10% |
| 封裝 | PDIP-40 (Plastic DIP, 40-pin) | PDIP-24 (Plastic DIP) |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| 安裝類型 | Through-Hole | — |
| Process Technology | CMOS (UV-erasable) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | — |
| Programming Method | UV-erase + Altera programmer (legacy) | — |
| Programmable Polarity | Yes (user-configurable output) | — |
| Output Enable Control | Yes (per-pin three-state) | — |
| Product Family | — | Classic EPLD |
| Usable Gates | — | 900 |
| Integration Gates (typical) | — | 4800 |
| Macrocells | — | 24 |
| Pin-to-Pin Delay (tPD) | — | 25 ns |
| Maximum Operating Frequency (fMAX) | — | 33.3 MHz |
| Technology | — | CMOS EPROM |
| 腳位數 | — | 24 |
| Dedicated Inputs | — | 10 |
| Dedicated I/O Pins | — | 12 |
| TTL Compatibility | — | 100% TTL emulation |
| Erasure Method | — | Not erasable in plastic package (windowless) |