EP910PI-40 vs EP910PI-35 比較
詳細並排比較 EP910PI-40 由 Altera 與 EP910PI-35 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP910PI-35 - 24-Macrocell Classic EPLD, 35ns, PDIP-40 | Rochester/Altera
EP910PI-35 ✓ 啟用中規格比較
| 參數 | EP910PI-40 | EP910PI-35 |
|---|---|---|
| 品牌 | Altera | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | 啟用中 |
| Device Family | Classic EPLD | Altera Classic EPLD (EP910) |
| Part Number | EP910PI-40 | — |
| Architecture | PAL-type macrocell, CMOS, UV-erasable | — |
| Number of Macrocells | 24 | — |
| Number of Dedicated Inputs | 12 | — |
| Number of I/O Lines | 24 | — |
| External Clock Inputs | 2 | — |
| 最大時脈頻率 | 25 MHz | — |
| Propagation Delay (tPD) | 43 ns | 35 ns |
| Speed Grade | -40 (43 ns) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (single supply) |
| 封裝 | PDIP-40 (Plastic DIP, 40-pin) | PDIP-40 (Plastic DIP, through-hole) |
| 工作溫度 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature grade] |
| 安裝類型 | Through-Hole | — |
| Process Technology | CMOS (UV-erasable) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | unknown |
| Programming Method | UV-erase + Altera programmer (legacy) | Legacy Altera programming interface (pre-JTAG) |
| Programmable Polarity | Yes (user-configurable output) | — |
| Output Enable Control | Yes (per-pin three-state) | — |
| Logic Elements | — | 24 Macrocells |
| Usable Gates | — | 450 |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Technology | — | CMOS, UV-erasable EPROM |
| I/O Pins | — | 24 bidirectional |
| Dedicated Inputs | — | 12 |
| Erasure Method | — | UV light (windowed variants) / One-time-programmable (this PI suffix) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |