EPC1213LC20 vs EPC1441LC20N 比較

詳細並排比較 EPC1213LC20 由 Intel 與 EPC1441LC20N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC1213LC20 EPC1441LC20N
品牌 Intel Intel
類別 EEPROM Memory ICs
生命週期狀態 Obsolete Obsolete
記憶體類型 OTP Configuration PROM (Flash-based) OTP EPROM (One-Time Programmable)
記憶體容量 212 Kbit 440 Kbit
介面 Serial (Altera FPGA configuration protocol) Serial, 4-wire (nCS, DCLK, DATA, nINIT_CONF)
Maximum Configuration Clock 6 MHz —
Supply Voltage (Core) 5.0 V —
I/O Voltage Tolerance 3.3 V / 5.0 V —
Programmability One-Time Programmable (OTP) via IEEE 1149.1 JTAG —
In-System Programmability Yes (5.0 V and 3.3 V ISP) —
Supported FPGA Families ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX
Compression Support Yes (FPGA decompresses bitstream during load) —
工作溫度 0C to +70C (Commercial) 0 C to +70 C (commercial)
封裝 20-PLCC (J-lead, 9x9 mm) 20-PLCC (J-Lead, 9 x 9 mm)
Package Code QCCJ —
安裝類型 Surface Mount Surface Mount (PLCC socket compatible)
RoHS 狀態 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
組織 — 55 K x 8 bit
Configuration Clock (DCLK) — 8 MHz maximum
Programming Interface — JTAG (IEEE 1149.1) / Altera Programming Unit
供應電壓 — 3.3 V (typical)
Cascadable — Yes (nCS daisy-chain)
MSL 等級 — [DATA_NEEDED: MSL level]
Lead-Free — [DATA_NEEDED: lead-free status]

資料表與資源

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