EPC16JC88 vs EPC16VC88 比較

詳細並排比較 EPC16JC88 由 Altera 與 EPC16VC88 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC16JC88 EPC16VC88
品牌 Altera Altera
類別 Memory ICs Memory ICs
生命週期狀態 NRND Obsolete
Manufacturer Altera (now Intel FPGA) —
Family Enhanced Configuration Device (EPC4 / EPC8 / EPC16) —
Device Function In-system programmable configuration PROM for SRAM-based FPGAs —
Density 16 Mbit —
Programmability In-system programmable via IEEE 1149.1 JTAG —
Configuration Interface Altera/Intel serial configuration (DCLK / DATA0 / nCONFIG / nSTATUS / CONF_DONE) —
封裝 88-ball UBGA (11 x 8 mm), JEDEC designation C88 88-pin CQFP
Operating Temperature Grade Industrial (J suffix) —
供應電壓 [DATA_NEEDED: VCC operating range] 3.3 V
Supported FPGA Families Altera/Intel Stratix, Cyclone, APEX, Arria (via configuration interface) —
Configuration Clock Driven by target FPGA during configuration 20 MHz typical (serial mode)
Programming Interface JTAG (IEEE 1149.1) 4-wire TCK/TMS/TDI/TDO —
Multi-Device Configuration Supports daisy-chain configuration of multiple FPGAs —
濕度敏感等級 (MSL) [DATA_NEEDED: MSL rating per JEDEC J-STD-020] —
RoHS 狀態 [DATA_NEEDED: RoHS compliance declaration] [DATA_NEEDED: RoHS compliance status]
Lead-Free [DATA_NEEDED: lead-free finish] [DATA_NEEDED: lead-free status]
無鹵素 [DATA_NEEDED: halogen-free status] —
Memory Density — 16 Mbit
Device Family — EPC16 Enhanced Configuration
介面 — Serial (1-bit) or Parallel (8-bit) configuration
JTAG Compliance — IEEE Std 1149.1
ISP Compliance — IEEE Std 1532 draft 2.0
Data Compression — Yes (FPGA-side decompression)
Cascade Support — Yes (multi-FPGA chains)
工作溫度 — -40 C to +85 C [DATA_NEEDED: commercial vs industrial grade]
安裝類型 — Surface Mount
MSL 等級 — [DATA_NEEDED: MSL classification]
Configuration Mode — Passive Serial, Passive Parallel, JTAG
Internal Controller — Yes (state-machine based)

資料表與資源

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