EPC16QC100DM vs EPC16Q100 比較

詳細並排比較 EPC16QC100DM 由 Intel 與 EPC16Q100 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC16QC100DM EPC16Q100
品牌 Intel Intel
類別 Memory ICs Memory ICs
生命週期狀態 NRND Obsolete
記憶體類型 Non-volatile Configuration PROM (NOR flash) Flash Configuration PROM
Memory Density 16 Mbit (2 Mbyte) —
Configuration Interface Serial (SPI-compatible, Altera FPP mode) Serial/parallel Altera FPGA configuration protocol
Core Supply Voltage (VCC) 3.0 V to 3.6 V —
I/O Voltage (VIO) 2.5 V / 3.3 V selectable —
Output Voltage (VPP) 1.8 V / 2.5 V / 3.3 V selectable —
Maximum DCLK Frequency 40 MHz —
Cascadable Yes (multi-device daisy chain via nCASC) —
In-System Programming Yes (IEEE 1532 / JTAG) —
Program/Erase Cycles [DATA_NEEDED: program/erase cycle endurance] —
Data Retention [DATA_NEEDED: data retention years] —
工作溫度範圍 -40 C to +85 C (industrial) —
封裝 100-pin PQFP (QFPA) 100-pin PQFP (20 x 14 mm)
Package Code Q100 + DM suffix —
Lead-Free / RoHS [DATA_NEEDED: lead-free status] —
Compatible FPGA Families Stratix, Cyclone, APEX, ACEX —
MSL 等級 [DATA_NEEDED: MSL rating] [DATA_NEEDED: MSL rating]
記憶體容量 — 16 Mb
供應電壓 — 3.3 V
Programmability — In-system programmable via JTAG (IEEE 1149.1)
I/O Voltage Tolerance — 3.3 V and 5 V tolerant
安裝類型 — Surface Mount
工作溫度 — -40C to +85C (industrial)
Write Protection — Hardware write protection pin
Configuration Clock — Dedicated DCLK output to FPGA
Compression Support — On-chip controller supports bitstream compression
JTAG Chain Support — Yes (multi-device chain capable)
RoHS 狀態 — Compliant (lead-free version)
Family — Altera Enhanced Configuration Device (EPC4/EPC8/EPC16)

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