EPC16QC100T vs EPC16QI100TBAC 比較

詳細並排比較 EPC16QC100T 由 Altera 與 EPC16QI100TBAC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EPC16QI100TBAC EPC16QI100TBAC - Altera Enhanced Configuration PROM 16Mb | FPGA

EPC16QI100TBAC - Altera Enhanced Configuration PROM 16Mb | FPGA

EPC16QI100TBAC ⚠ 最後購買機會

規格比較

參數 EPC16QC100T EPC16QI100TBAC
品牌 Altera Altera
類別 Memory ICs Memory ICs
生命週期狀態 NRND 最後購買
記憶體類型 In-System Programmable Configuration PROM Flash (Enhanced Configuration Device)
記憶體容量 16 Mbit —
介面 Serial FPGA configuration + JTAG (IEEE 1149.1) —
Supply Voltage (VCC) 3.3 V —
Programmability In-System Programmable via JTAG —
Daisy-Chain Support Yes (multi-device cascade) —
Data Compression Built-in decompression engine (up to 35% expansion) Supported (15-30% density gain depending on target FPGA)
FPGA Compatibility Altera Cyclone, Stratix, ACEX, APEX series —
封裝 PQFP-100 (20 x 14 mm) 100-pin PQFP (20 x 14 mm)
安裝類型 Surface Mount Surface Mount (PQFP)
工作溫度 0C to +70C (commercial) -40C to +85C (industrial)
Lead-Free / RoHS Depends on date code; verify per lot Lead-free (per JEDEC J-STD-020); RoHS compliance: [DATA_NEEDED]
MSL 等級 3 (per JEDEC J-STD-020) 3 (168 hours)
Programming Cycles 100 typical (per Altera datasheet) —
Packaging Suffix 'T' indicates Tape and Reel —
Max DCLK Frequency [DATA_NEEDED: max DCLK frequency] —
Access Time [DATA_NEEDED: serial access time] —
Memory Density — 16 Mbit (2 Mbyte)
供應電壓 — 3.3 V
Configuration Modes — Passive Parallel Synchronous (PPS), Passive Parallel Asynchronous (PPA), Passive Serial (PS)
Maximum Configuration Clock — 40 MHz
Number of Configuration Pages — Up to 8 (selectable via PGM[2..0])
In-System Programmable — Yes (via JTAG / IEEE 1149.1)
JTAG Support — Yes (IEEE 1149.1 boundary-scan and programming)
Supported FPGA Families — Altera Stratix, Cyclone, Arria series
Dynamic Reconfiguration — Yes (page mode via PGM[2..0] pins)
Configuration Controller — Integrated
Programming Interface — JTAG / 4-wire passive serial

資料表與資源

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