EPC16QI100T vs EPC18QI100 比較

詳細並排比較 EPC16QI100T 由 Altera 與 EPC18QI100 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC16QI100T EPC18QI100
品牌 Altera Altera
類別 FPGA & CPLD Memory ICs
生命週期狀態 Obsolete Obsolete
Product Type Enhanced Configuration PROM (Flash) —
記憶體容量 16 Mbit —
供應電壓 3.3 V —
Configuration Data Width Serial or 8-bit parallel (FPGA mode dependent) —
Programmable Interface IEEE 1149.1 JTAG (in-system programmable) —
Compression Support Yes (Altera FPGA-side decompression) —
Page-Mode Configuration Yes (multi-device daisy chain) —
Supported FPGAs Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K —
工作溫度 -40C to +85C (industrial) —
封裝 100-pin PQFP (Plastic Quad Flat Pack), 20x14 mm 100-pin PQFP (Plastic Quad Flat Pack)
安裝類型 Surface Mount Surface Mount
Shipping Media Tape and Reel (suffix T) —
Configuration Controller Built-in (nCONFIG, nSTATUS, CONF_DONE handshake) —
RoHS 狀態 [DATA_NEEDED: RoHS compliance] Compliant (Pb-free part marking)
MSL 等級 [DATA_NEEDED: MSL rating] [DATA_NEEDED: MSL level]
Manufacturer — Altera (now Intel Programmable Solutions Group)
Device Type — FPGA Configuration PROM (nonvolatile)
Memory Density — 18 Mbit (18,874,368 bits)
Configuration Interface — Altera serial (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE)
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V or 5 V tolerant
Programming Interface — JTAG (IEEE 1149.1) in-system programmable
Cascading Support — Yes (via nCASC pin, multi-device chains supported)
Package Dimensions — 14 mm x 20 mm x 1.4 mm (body) / 3.4 mm (overall incl. leads)
工作溫度範圍 — -40 C to +85 C (industrial)
Lead Finish — Matte tin (lead-free, per Altera Pb-free roadmap)
Configuration Time — [DATA_NEEDED: configuration time at typical DCLK]
End-of-Life Status — Obsolete; replaced by Altera/Intel EPCQ family

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