EPC1LC120 vs EPC1LC20 比較
詳細並排比較 EPC1LC120 由 Altera 與 EPC1LC20 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC1LC120 | EPC1LC20 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | 啟用中 | Obsolete |
| 記憶體類型 | Serial Configuration Memory (Flash-based, non-volatile) | Non-volatile configuration memory (Flash/EPROM) |
| Memory Density | 1 Mbit | — |
| Serial Clock Frequency (DCLK) | 8 MHz | — |
| Supported FPGA Families | APEX 20K, ACEX 1K, Cyclone, MAX, Mercury, Stratix-class | — |
| 介面 | Altera / Intel proprietary FPGA-configuration serial bus (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) | — |
| 封裝 | LQFP-120 (Low-profile Quad Flat Pack) | 20-pin PLCC (J-leaded, surface mount) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度範圍 | [DATA_NEEDED: operating temperature range] | — |
| 供應電壓 | [DATA_NEEDED: VCC range] | 3.3 V or 5.0 V |
| Programming | Factory / JTAG via Altera programming tools | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| MSL 等級 | [DATA_NEEDED: MSL rating] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Configuration Mode | Serial configuration of SRAM-based FPGAs | Serial, multi-device daisy-chain capable |
| Compatible Bitstream Width | Serial | — |
| Memory Capacity | — | 1 Mbit (1,048,576 bits) |
| 介面類型 | — | Serial configuration interface |
| Maximum DCLK Frequency | — | 8 MHz |
| In-System Programmability | — | Yes (IEEE 1149.1 / JTAG) |
| Programmable Voltage | — | 5.0 V and 3.3 V ISP |
| 腳位數 | — | 20 |
| 工作溫度 | — | [DATA_NEEDED: Operating temperature range] |
| Compatible FPGA Families | — | ACEX 1K, APEX 20K, FLEX 10K, Cyclone, Mercury |
| JTAG Pins | — | TCK, TMS, TDI, TDO |