EPC1LC20AL3894 vs EPC1LC20-W 比較

詳細並排比較 EPC1LC20AL3894 由 Intel 與 EPC1LC20-W 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC1LC20AL3894 EPC1LC20-W
品牌 Intel Altera
類別 Memory ICs Memory ICs
生命週期狀態 Obsolete Obsolete
記憶體類型 OTP Configuration PROM (EPROM-based) OTP (One-Time Programmable) Configuration PROM
Memory Capacity 1 Mbit (212,942 × 1-bit) —
Supply Voltage (VCC) 3.0 V to 3.6 V (3.3 V nominal) —
Configuration Clock Frequency Up to 8 MHz —
Configuration Interface Serial (Altera standard 4-wire: DATA, DCLK, nCS, nINIT_CONF) —
封裝 20-pin PLCC (J-lead) 20-PLCC J-lead (9x9 mm)
Package Dimensions 9.0 × 9.0 × 4.5 mm (PLCC-20) —
工作溫度 -40 °C to +85 °C (industrial) —
Programming Method Factory / Altera programming service (one-time only) —
Erasure Windowed package supports UV erase (ceramic DIP variant); PLCC is OTP —
輸出配置 Serial data out on DCLK rising edge —
Compatible FPGA Families APEX, ACEX, FLEX 10K, MAX 7000S/AE/B, Cyclone (legacy) —
安裝類型 Surface Mount / Socket (PLCC socket compatible) Surface Mount (PLCC socket or direct solder)
RoHS 狀態 Unknown — verify with manufacturer Compliant (Pb-free -W finish)
生命週期狀態 Obsolete (EOL announced by Altera / Intel PSG) —
Shipping Variant Suffix AL3894 (tape-and-reel / specific Altera part marking) —
記憶體容量 — 1 Mbit
Configuration Clock (DCLK) — 8 MHz maximum
供應電壓 — 3.3 V and 5.0 V
介面 — Altera serial configuration (DCLK / DATA / nCONFIG / nSTATUS)
In-System Programming — Yes - IEEE 1149.1 (JTAG) ISP at 3.3 V / 5.0 V
Lead Finish — Pb-free (matte tin) - "-W" suffix
Daisy-Chain Support — Yes - multiple EPC1 / EPC2 devices cascade to program larger FPGAs
Compression Support — Yes - stores compressed Altera FPGA bitstreams
工作溫度範圍 — [DATA_NEEDED: operating temperature range]
Programming Cycles — 1 (OTP)
Target FPGA Families — Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K, Mercury

資料表與資源

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