EPC2-TI32 vs EPC2TI32N 比較

詳細並排比較 EPC2-TI32 由 Altera 與 EPC2TI32N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC2-TI32 EPC2TI32N
品牌 Altera Altera
類別 Memory ICs Memory ICs
生命週期狀態 Obsolete Obsolete
記憶體類型 In-System Programmable Configuration PROM In-System Programmable Configuration PROM (Flash)
記憶體容量 1.6 Mbit 1.6 Mbit
介面 Serial configuration, 10 MHz —
供應電壓 3.3 V —
I/O Tolerance 5 V tolerant —
封裝 32-pin TQFP (7x7 mm) —
安裝類型 Surface Mount Surface Mount
Programming Interface JTAG (IEEE 1149.1) —
Supported FPGA Families ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, Mercury, FLEX 10K
Configuration Pins nCONFIG, nSTATUS, CONF_DONE (open-drain) nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA[7:0]
Multi-Device Daisy-Chain Support Yes —
工作溫度 [DATA_NEEDED: Operating temperature range] -40C to +85C
RoHS 狀態 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: Lead-free status] —
MSL 等級 [DATA_NEEDED: MSL rating] —
Programmable Type — In System Programmable (ISP via JTAG)
介面類型 — Parallel configuration data output + JTAG (IEEE 1149.1) ISP
Supply Voltage - 3.3V Mode — 3.0 V to 3.6 V
Supply Voltage - 5V Mode — 4.5 V to 5.5 V
封裝 / 外殼 — 32-TQFP (7x7 mm)
Packaging — Tray
JTAG Interface — Yes (IEEE 1149.1 compliant TAP for ISP)
Lead Free — [DATA_NEEDED: lead-free status]

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