EPC2L120 vs EPC2CC20N 比較
詳細並排比較 EPC2L120 由 Altera 與 EPC2CC20N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC2L120 | EPC2CC20N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | Memory ICs | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| 記憶體類型 | Configuration PROM (Flash-based) | — |
| Density | 120 Kbit | [DATA_NEEDED: bitstream density in bits] |
| Configuration Interface | Serial, FPGA-targeted | 16-bit parallel (FPP) / Passive Serial (PS) |
| Operating Voltage | 2.7 V to 3.6 V (3.3 V typ) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| 封裝 | PLCC-20 | PLCC-20 |
| Compatible FPGAs | Altera Cyclone, Cyclone II, APEX-series | — |
| 工作溫度 | -40 C to +85 C | [DATA_NEEDED: industrial/commercial temp range] |
| CONF_DONE Output | Open-drain, wire-OR capable | — |
| Data Retention | 20 years (per Altera datasheet family) | — |
| Program/Erase Cycles | 100 cycles minimum | — |
| 安裝類型 | Surface Mount | Surface Mount (PLCC-20 socket compatible) |
| RoHS 狀態 | unknown | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | unknown | — |
| Family | EPC2 (Enhanced Configuration) | — |
| 功能 | — | Configuration device for SRAM-based LUT FPGAs |
| Supply Voltage (VCC) | — | 3.3 V |
| Programming Interface | — | JTAG (IEEE 1149.1) via ByteBlasterMV / USB-Blaster |
| In-System Programmable | — | Yes |
| Error Detection | — | 16-bit CRC on configuration frames |
| Configuration Modes Supported | — | FPP and PS (depends on host FPGA) |
| Cascadable | — | Yes (multiple EPC2 devices for larger bitstreams) |
| Open-Drain Status Pin | — | Yes (CONF_DONE / nSTATUS compatible) |
| MSL 等級 | — | [DATA_NEEDED: MSL rating] |