EPC2L20U vs EPC2LI20U 比較

詳細並排比較 EPC2L20U 由 Altera 與 EPC2LI20U 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EPC2L20U EPC2L20U - 1.6Mb Configuration PROM 20-PLCC | Altera

EPC2L20U - 1.6Mb Configuration PROM 20-PLCC | Altera

EPC2L20U ⚠ 最後購買機會

規格比較

參數 EPC2L20U EPC2LI20U
品牌 Altera Altera
類別 FPGA & CPLD Memory ICs
生命週期狀態 最後購買 Obsolete
記憶體容量 1.6 Mbit 1.6 Mbit (65,536 x 1-bit device)
Supply Voltage (VCC) 3.0 V to 3.6 V 3.0 V to 5.5 V (5.0 V nominal)
介面類型 Serial configuration (DCLK/DATA0) —
Programmability In-system programmable via IEEE 1532 / JTAG In-system programmable via JTAG (IEEE 1149.1)
Supported FPGAs APEX II, APEX 20K, Mercury, Stratix, Cyclone, ACEX 1K —
Configuration Mode Single + Cascade (multi-PROM daisy chain) —
Compression Support Yes (FPGA decompresses bitstream) —
工作溫度 -40C to +85C (industrial) —
封裝 20-PLCC (PLCC-20) 20-pin PLCC (9x9 mm)
安裝類型 Surface Mount / Socket Surface Mount (PLCC socket)
JTAG Support Yes (IEEE Std 1149.1 boundary scan) —
腳位數 20 —
RoHS 狀態 [DATA_NEEDED: RoHS status] [DATA_NEEDED: rohs status]
Lead-Free [DATA_NEEDED: lead-free status] —
MSL 等級 [DATA_NEEDED: MSL level] [DATA_NEEDED: MSL moisture sensitivity level]
記憶體類型 — Configuration PROM (serial EEPROM)
Programming Voltage — 5.0 V (via internal charge pump)
Configuration Interface — Serial 4-pin (DATA, DCLK, nCS, OE)
Maximum DCLK Frequency — 33 MHz (fast mode)
工作溫度範圍 — -40 C to +85 C (industrial)
Cascade Support — Yes (via nCASC pin)
Device ID — 32-bit JTAG-readable
Supported FPGA Families — APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 6000/10KE/10KA

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