EPC2LC20CAD vs EPC2C20 比較
詳細並排比較 EPC2LC20CAD 由 Altera 與 EPC2C20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC2LC20CAD | EPC2C20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | Memory ICs | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 啟用中 |
| 記憶體類型 | Configuration PROM (Flash) | — |
| Memory Capacity | 1.6 Mbit | — |
| 供應電壓 | 3.3 V (nominal) | — |
| I/O Voltage Tolerance | 5 V tolerant | — |
| Configuration Mode | Serial (bit-wide, Altera FPGAs) | [DATA_NEEDED: configuration mode] |
| Program Interface | IEEE Std 1149.1 JTAG (in-system programmable) | — |
| 封裝 | 20-pin J-lead PLCC (PLCC-20) | [DATA_NEEDED: package] |
| 腳位數 | 20 | [DATA_NEEDED: pin count] |
| 工作溫度 | -40C to +85C (commercial) | — |
| Maximum Input Voltage (DC) | -0.3 V to +7.0 V | — |
| Input Undershoot/Overshoot | -2.0 V to +7.0 V for <100 mA, <20 ns no-load | — |
| Compatible FPGA Families | APEX 20K, ACEX 1K, Cyclone, Stratix | — |
| Programming Method | JTAG ISP (no external programmer required) | — |
| RoHS 狀態 | Compliant | [DATA_NEEDED: RoHS status] |
| 安裝類型 | Surface Mount / Through-hole (PLCC socket) | — |
| Manufacturer | — | Altera |
| MPN | — | EPC2C20 |
| Device Type | — | Configuration device integrated circuit |
| Primary Function | — | Configuration of SRAM-based lookup-table devices |
| Configuration Architecture | — | Single-device configuration solution |
| Architecture Block 1 | — | Configuration controller |
| Architecture Block 2 | — | Flash memory |
| Memory Technology | — | Flash memory |
| Supported Device Class | — | SRAM-based LUT devices |
| Memory Density | — | [DATA_NEEDED: memory density] |
| Configuration Data Interface | — | [DATA_NEEDED: configuration data interface] |
| Operating Voltage | — | [DATA_NEEDED: operating voltage] |
| Configuration Clock Frequency | — | [DATA_NEEDED: configuration clock frequency] |
| 工作溫度範圍 | — | [DATA_NEEDED: operating temperature range] |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |