EPC2LC20NA vs EPC2LC20NU 比較

詳細並排比較 EPC2LC20NA 由 Altera 與 EPC2LC20NU 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EPC2LC20NA EPC2LC20NA - 1.6Mb ISP Config PROM | Altera | PLCC-20

EPC2LC20NA - 1.6Mb ISP Config PROM | Altera | PLCC-20

EPC2LC20NA ⚠ 最後購買機會

規格比較

參數 EPC2LC20NA EPC2LC20NU
品牌 Altera Altera
類別 Memory ICs Memory ICs
生命週期狀態 最後購買 Obsolete
Manufacturer Altera Corporation (Intel Programmable Solutions Group) —
記憶體類型 Configuration PROM (Flash-based, ISP) —
Memory Density 1.6 Mbit 1.6 Mbit
Operating Voltage (VCC) 3.3 V —
介面 Serial (passive-serial) data output to FPGA —
Programmability In-system programmable via IEEE 1532 JTAG —
封裝 20-pin PLCC (9x9 mm) 20-pin J-lead PLCC (9x9 mm)
安裝類型 Surface Mount (PLCC socket compatible) Surface Mount
工作溫度 -40C to +85C (industrial grade) 0C to +70C (commercial)
Supported FPGA Families APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, Cyclone, Mercury —
JTAG Compliance IEEE Std 1149.1 / IEEE 1532 —
Configuration Mode Passive Serial (PS) —
RoHS 狀態 [DATA_NEEDED: rohs status] —
Daisy-Chain Support Yes —
Recommended Companion FPGA Altera Cyclone, FLEX 10K, APEX 20K series —
功能 — In-System Programmable Configuration PROM
FPGA Interface — Altera serial (4-pin: nCS, DCLK, DATA, nINIT_CONF)
Supply Voltage (VCC) — 3.0 V to 3.6 V
I/O Tolerance — 5 V tolerant inputs (per datasheet, except JTAG pins)
Programming Method — In-system via IEEE 1149.1 JTAG
JTAG Support — Yes (IEEE Std 1149.1 boundary-scan compliant)
Cascade Support — Yes - daisy-chain for larger bitstreams
Minimum DC Input — -0.3 V (inputs may undershoot to -2.0 V for <20 ns)
Maximum Overshoot — 7.0 V for <100 mA and <20 ns
Lead-Free / RoHS — Non-LEAD / non-RoHS (NU suffix = matte tin Sn finish, not Pb-free)
Compatibility — Altera APEX 20K, APEX II, Mercury, FLEX 10K, ACEX 1K, Cyclone (legacy serial configuration)

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