EPC2T32U vs EPC2T132U 比較

詳細並排比較 EPC2T32U 由 Altera 與 EPC2T132U 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC2T32U EPC2T132U
品牌 Altera Intel
類別 Memory ICs Memory ICs
生命週期狀態 Obsolete Obsolete
功能 Configuration PROM for SRAM-based LUT FPGAs —
Memory Density 1.6 Mbit —
供應電壓 3.3 V or 5.0 V (user-selectable) 3.3 V
Programmability In-system programmable via JTAG (IEEE 1149.1) —
Configuration Modes Supported Passive serial, passive parallel synchronous, passive parallel asynchronous, JTAG —
封裝 32-pin TQFP 132-pin UQFP (Ultra-thin Quad Flat Pack)
工作溫度 Commercial / Industrial grade [DATA_NEEDED: exact range] [DATA_NEEDED: operating temperature range]
Cascading Support Yes, via dedicated cascade port for density expansion —
Compression Support Altera bitstream decompression (up to 50% storage reduction) —
Compatible FPGA Families APEX II, APEX 20K, Mercury, ACEX 1K —
Lead-Free Finish Yes (per part suffix 'U') —
安裝類型 Surface Mount Surface Mount
MSL 等級 [DATA_NEEDED: MSL rating] [DATA_NEEDED: MSL level]
RoHS 狀態 Compliant [DATA_NEEDED: RoHS status]
Hand-shake Pins nSTATUS, nCONFIG, CONF_DONE —
Manufacturer — Intel (formerly Altera)
Product Type — FPGA Configuration Device (Boot PROM)
Target FPGAs — Altera APEX II, Cyclone, Stratix, and other SRAM-based LUT FPGAs
Configuration Memory Size — [DATA_NEEDED: configuration memory size in bits]
介面 — Serial (Passive Serial), JTAG (IEEE 1149.1), Passive Parallel
In-System Programmability — Yes (via JTAG)
JTAG Support — Yes (IEEE 1149.1 compliant TAP)
Configuration Clock — Internal oscillator (no external crystal required)
Data Compression — Yes (up to 2x compression vs competing PROMs)
Lead-Free — [DATA_NEEDED: lead-free status]
生命週期狀態 — Obsolete (per Altera/Intel product discontinuance)
Compatible Quartus Version — [DATA_NEEDED: Quartus version supporting EPC2]

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