EPC2T32U vs EPC2T32 比較

詳細並排比較 EPC2T32U 由 Altera 與 EPC2T32 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC2T32U EPC2T32
品牌 Altera Altera
類別 Memory ICs Memory ICs
生命週期狀態 Obsolete NRND
功能 Configuration PROM for SRAM-based LUT FPGAs —
Memory Density 1.6 Mbit —
供應電壓 3.3 V or 5.0 V (user-selectable) 3.3 V (5 V tolerant I/O per datasheet)
Programmability In-system programmable via JTAG (IEEE 1149.1) In-System Programmable (ISP) via JTAG
Configuration Modes Supported Passive serial, passive parallel synchronous, passive parallel asynchronous, JTAG —
封裝 32-pin TQFP 32-pin TQFP (7x7 mm)
工作溫度 Commercial / Industrial grade [DATA_NEEDED: exact range] -40C to +85C (industrial)
Cascading Support Yes, via dedicated cascade port for density expansion —
Compression Support Altera bitstream decompression (up to 50% storage reduction) —
Compatible FPGA Families APEX II, APEX 20K, Mercury, ACEX 1K —
Lead-Free Finish Yes (per part suffix 'U') —
安裝類型 Surface Mount Surface Mount
MSL 等級 [DATA_NEEDED: MSL rating] [DATA_NEEDED: MSL level]
RoHS 狀態 Compliant Compliant
Hand-shake Pins nSTATUS, nCONFIG, CONF_DONE —
Product Type — FPGA Configuration PROM (non-volatile boot memory)
記憶體容量 — 1.6 Mbit
Configuration Interface — Serial
最大時脈頻率 — 10 MHz
JTAG Support — Yes (IEEE 1149.1 boundary-scan + ISP)
Supported FPGA Families — APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K
Cascadable — No (single-device configuration only)
Lead-Free — Yes
Configuration Mode — Serial (DCLK/DATA/nCS)
Document Size (third-party) — 26 pages (per alldatasheet listing)

資料表與資源

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