EPC2TC32N vs EPC2-TC32 比較
詳細並排比較 EPC2TC32N 由 Altera 與 EPC2-TC32 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC2TC32N | EPC2-TC32 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | Obsolete | 最後購買 |
| Manufacturer | Altera (now Intel) | — |
| 記憶體類型 | Flash Configuration PROM | EPROM (OTP/UV-erasable configuration PROM) |
| 記憶體容量 | 1.6 Mbit | 1.6 Mbit |
| Programmable Type | In System Programmable (ISP) | — |
| 介面 | JTAG (IEEE 1149.1) + serial/parallel | — |
| Supply Voltage - VCCINT | 3.0 V to 3.6 V or 4.75 V to 5.25 V | — |
| Supply Voltage - VCCIO | 3.0 V to 3.6 V or 4.75 V to 5.25 V | — |
| Max Configuration Clock | 8 MHz | — |
| 封裝 | 32-TQFP (7x7 mm) | 32-pin TQFP (7x7 mm) |
| 工作溫度 | 0 °C to +70 °C (Commercial) | — |
| Supported FPGA Families | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX | Stratix I/II, Cyclone I/II, APEX 20K/II, Mercury, ACEX 1K, FLEX 10K |
| Daisy-Chain Support | Yes (multi-FPGA cascade) | — |
| JTAG Compliance | IEEE 1149.1 | — |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status - datasheet does not specify in retrieved snippet] |
| Configuration Mode | Serial (AS) or Parallel (PS/AP) | Serial (FPP/MSD via FPGA master/slave) |
| 介面類型 | — | Serial |
| 組織 | — | Serial bitstream output |
| Programmability | — | In-System Programmable (ISP) via JTAG (IEEE 1149.1) |
| 供應電壓 | — | 3.3 V |
| 工作溫度範圍 | — | 0C to +70C (Commercial) |
| Output Control | — | OE and nCS gating internal tri-state buffer |
| Internal Oscillator | — | Yes (drives address counter) |
| MSL 等級 | — | MSL 3 (168 hours) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |