EPC2TC32UCAF48 vs EPC2LC20N 比較

詳細並排比較 EPC2TC32UCAF48 由 Altera 與 EPC2LC20N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC2TC32UCAF48 EPC2LC20N
品牌 Altera Intel
類別 FPGA & CPLD Memory ICs
生命週期狀態 Obsolete NRND
單價 (USD) — $7.40
記憶體容量 1.6 Mb 1.6 Mbit
Device Family EPC2 (Enhanced Configuration Device) —
Programmability In-system programmable (ISP) via JTAG —
介面 4-wire serial (nCS, DCLK, DATA, nINIT_CONF) + JTAG Serial (DATA0, DCLK, nCONFIG, nSTATUS, CONF_DONE)
Supply Voltage (VCC) 3.3 V nominal —
FPGA Compatibility Altera SRAM-based LUT FPGAs (Cyclone, Stratix, APEX, ACEX, FLEX, MAX 9000) —
Cascading Supported for bitstreams larger than 1.6 Mb —
封裝 32-pin TQFP (CAF48 designation per Altera ordering code) 20-pin PLCC (J-Lead, 9x9 mm)
工作溫度 [DATA_NEEDED: commercial 0-70C vs industrial -40-85C variant] [DATA_NEEDED: operating temperature range]
Data Retention 10 years typical (EEPROM-based) —
Programming Cycles 100 cycles minimum (EEPROM endurance) —
Process Technology CMOS EEPROM —
安裝類型 Surface Mount Surface Mount
MSL 等級 [DATA_NEEDED: MSL classification] —
RoHS 狀態 [DATA_NEEDED: per ordering code; older CAF48 lots were non-RoHS] [DATA_NEEDED: RoHS status]
功能 — In-System Programmable Configuration PROM for SRAM-based FPGAs
記憶體類型 — Flash
Programmable Type — In System Programmable (ISP)
Supply Voltage VCCINT — 3.0 V to 3.6 V
Supply Voltage VCCIO — 4.75 V to 5.25 V
Configuration Clock Frequency — 8 MHz (max)
JTAG Support — IEEE 1149.1 / IEEE 1532 compliant
Packaging — Tube
Supported FPGA Families — Altera APEX, Cyclone, Stratix, ACEX, MAX 7000

資料表與資源

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