EPC2TC32V vs EPC8QC100 比較

詳細並排比較 EPC2TC32V 由 Altera 與 EPC8QC100 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC2TC32V EPC8QC100
品牌 Altera Altera
類別 Memory ICs Memory ICs
生命週期狀態 NRND Obsolete
記憶體類型 In-System Programmable Configuration PROM Configuration PROM (Flash-based)
記憶體容量 1.6 Mbit 8 Mbit
組織 x8 (configurable serial/parallel output) —
Supply Voltage (VCC) 3.0 V to 3.6 V (3.3 V nominal) —
I/O Voltage Tolerance 5 V tolerant —
介面 Passive Serial (PS), Passive Parallel Async (PPA), Passive Parallel Sync (PPS), JTAG ISP —
Programming Method In-system via JTAG (IEEE 1149.1) —
Cascadable Yes (multiple EPC2s daisy-chain for larger bitstreams) —
工作溫度 0 C to +70 C (commercial) 0C to +70C (Commercial)
封裝 32-pin TQFP (7 mm x 7 mm) 100-Pin PQFP (20 x 14 mm)
安裝類型 Surface Mount Surface Mount
MSL 等級 [DATA_NEEDED: MSL level] —
Compatible FPGA Families APEX 20K, APEX II, FLEX 10K/10KE, ACEX 1K, Cyclone (original), Stratix (original) Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K
Configuration Hand-shake Pins nCONFIG, nSTATUS, CONF_DONE, DCLK —
RoHS 狀態 Compliant [DATA_NEEDED: RoHS compliance]
Lead-Free Yes —
Flash Access Time — 90 ns (~10 MHz)
Configuration Bus Width — 16-bit (DQ[])
Configuration Bandwidth — Up to 160 Mbps
Decompression Support — Yes (Altera proprietary)
Supported Configuration Modes — FPP, PS, AS (FPGA-dependent)
ISP Interface — JTAG (IEEE 1149.1)
供應電壓 — 3.3 V
Lead Free — [DATA_NEEDED: lead-free status]

資料表與資源

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