EPC4Q100N vs EPC4Q100T 比較
詳細並排比較 EPC4Q100N 由 Intel 與 EPC4Q100T 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC4Q100N | EPC4Q100T |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| 記憶體類型 | Flash (NOR, Enhanced Configuration Device) | Flash (non-volatile) |
| 記憶體容量 | 4 Mbit (512 Kbyte) | 4 Mbit |
| Configuration Interface | Serial (FLEX) / Parallel / JTAG ISP | — |
| 供應電壓 | 3.3 V | — |
| Program/Erase Cycles | [DATA_NEEDED: minimum endurance in cycles] | — |
| 封裝 | 100-pin PQFP | — |
| 安裝類型 | Surface Mount | — |
| 工作溫度 | -40 C to +85 C (industrial) | — |
| JTAG Support | IEEE 1149.1 compliant | — |
| In-System Programmable | Yes | — |
| Target FPGA Families | Cyclone, Stratix, APEX, Mercury, ACEX | — |
| Data Width (parallel mode) | 8-bit | — |
| Lead-Free / RoHS | [DATA_NEEDED: per lot] | — |
| Status | Not Recommended for New Designs (NRND) | — |
| Configuration Schemes | Active Serial (AS) / Active Parallel (AP) / Passive Serial (PS) | — |
| MSL 等級 | [DATA_NEEDED: per JEDEC J-STD-020] | — |
| 功能 | — | Enhanced Configuration Device for SRAM-based LUT FPGAs |
| Configuration Modes Supported | — | PS, FPP (16-bit), AS |
| Flash Access Time | — | 90 ns (approx 10 MHz core clock) |
| Maximum Configuration Data Rate | — | 160 Mbps (FPP, 16-bit bus) |
| 資料匯流排寬度 | — | 16-bit (DQ[15:0]) |
| In-System Programming | — | Yes (JTAG IEEE 1149.1) |
| Supply Voltage (Core) | — | 3.3 V |
| I/O Voltage Tolerance | — | 3.3 V (5 V tolerant on legacy interface pins) |
| Package Type | — | PQFP-100 (Plastic Quad Flat Pack) |
| Package Dimensions | — | 20 x 14 mm |
| 工作溫度範圍 | — | [DATA_NEEDED: operating temperature range] |
| Compatible FPGA Families | — | Stratix, Cyclone, APEX, Mercury, ACEX |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS status] |
| Manufacturer | — | Intel (formerly Altera) |