EPC4QI100N vs EPC4Q100T 比較

詳細並排比較 EPC4QI100N 由 Altera 與 EPC4Q100T 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC4QI100N EPC4Q100T
品牌 Altera Intel
類別 Memory ICs FPGA & CPLD
生命週期狀態 啟用中 NRND
單價 (USD) $10.40 —
記憶體類型 In-System Programmable Configuration PROM (NOR flash) Flash (non-volatile)
記憶體容量 4 Mbit (4,194,304 bits) 4 Mbit
Programmable Type In System Programmable (ISP via JTAG) —
Supply Voltage (VCC) 3.0 V to 3.6 V —
介面 Altera serial (x1) configuration + JTAG —
Configuration Clock DCLK [DATA_NEEDED: DCLK maximum frequency] —
Active Supply Current (ICC active) [DATA_NEEDED: ICC active typical value] —
Standby Supply Current [DATA_NEEDED: ICC standby typical value] —
工作溫度 -40C to +85C (industrial) —
Storage Temperature -65C to +150C —
封裝 100-pin PQFP (PowerPQFP, 20x14 mm) —
Package Code QI100 (PQFP-100, industrial) —
安裝類型 Surface Mount —
MSL 等級 [DATA_NEEDED: MSL rating] —
RoHS 狀態 [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status]
JTAG Standard IEEE 1149.1 boundary-scan / ISP —
Cascading Supported (multi-device daisy chain) —
Target FPGAs Altera Cyclone, Cyclone II, Stratix series —
功能 — Enhanced Configuration Device for SRAM-based LUT FPGAs
Configuration Modes Supported — PS, FPP (16-bit), AS
Flash Access Time — 90 ns (approx 10 MHz core clock)
Maximum Configuration Data Rate — 160 Mbps (FPP, 16-bit bus)
資料匯流排寬度 — 16-bit (DQ[15:0])
In-System Programming — Yes (JTAG IEEE 1149.1)
Supply Voltage (Core) — 3.3 V
I/O Voltage Tolerance — 3.3 V (5 V tolerant on legacy interface pins)
Package Type — PQFP-100 (Plastic Quad Flat Pack)
Package Dimensions — 20 x 14 mm
工作溫度範圍 — [DATA_NEEDED: operating temperature range]
Compatible FPGA Families — Stratix, Cyclone, APEX, Mercury, ACEX
Manufacturer — Intel (formerly Altera)

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