EPC8Q100 vs EPC16Q100 比較

詳細並排比較 EPC8Q100 由 Altera 與 EPC16Q100 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC8Q100 EPC16Q100
品牌 Altera Intel
類別 FPGA & CPLD Memory ICs
生命週期狀態 Obsolete Obsolete
Memory Density 8 Mbit (8,388,608 bits) —
記憶體類型 NOR Flash, One-Time-Programmable (OTP) via JTAG Flash Configuration PROM
Configuration Interface Altera EPC serial (DATA, DCLK, nCS, nINIT_CONF, nSTATUS, DONE) Serial/parallel Altera FPGA configuration protocol
Supply Voltage VCC 5.0 V (3.3 V core generated on-chip) —
Internal Core Voltage 3.3 V (on-chip LDO) —
Maximum EPC Clock 33 MHz —
Programmability In-system via IEEE 1149.1 JTAG In-system programmable via JTAG (IEEE 1149.1)
FPGA Compatibility APEX 20K, APEX II, Cyclone, Cyclone II, Stratix, Stratix GX —
Configuration Mode Support FPP, PS, AS, JTAG (FPGA-dependent) —
Program/Erase Endurance [DATA_NEEDED: cycle count] —
Data Retention [DATA_NEEDED: minimum years] —
工作溫度範圍 0 C to +70 C (commercial) —
Storage Temperature Range [DATA_NEEDED: range] —
封裝 100-pin PQFP (20 x 14 mm) 100-pin PQFP (20 x 14 mm)
安裝類型 Surface Mount Surface Mount
MSL 等級 [DATA_NEEDED: level] [DATA_NEEDED: MSL rating]
Lead-Free / RoHS [DATA_NEEDED: status] —
記憶體容量 — 16 Mb
供應電壓 — 3.3 V
I/O Voltage Tolerance — 3.3 V and 5 V tolerant
工作溫度 — -40C to +85C (industrial)
Write Protection — Hardware write protection pin
Configuration Clock — Dedicated DCLK output to FPGA
Compression Support — On-chip controller supports bitstream compression
JTAG Chain Support — Yes (multi-device chain capable)
RoHS 狀態 — Compliant (lead-free version)
Family — Altera Enhanced Configuration Device (EPC4/EPC8/EPC16)

資料表與資源

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