EPC8Q100C vs EPC8C100T 比較

詳細並排比較 EPC8Q100C 由 Altera 與 EPC8C100T 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EPC8Q100C EPC8Q100C - 8Mb Enhanced Configuration Device | Altera/Intel

EPC8Q100C - 8Mb Enhanced Configuration Device | Altera/Intel

EPC8Q100C ⚠ 最後購買機會

規格比較

參數 EPC8Q100C EPC8C100T
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 最後購買 Obsolete
Memory Density 8 Mbit 8 Mbit
Device Family Enhanced Configuration Device (EPC8Q100 series) —
Configuration Interface Serial / Parallel (x8) slave mode —
供應電壓 3.3 V (typ) 3.3 V
In-System Programming IEEE 1149.1 JTAG —
封裝 100-pin PQFP (20 x 14 mm) 100-pin PQFP (20 x 14 mm)
工作溫度 0 C to +70 C (commercial, 'C' suffix) -40C to +85C (industrial)
Cascade Support Up to 4 devices cascadable Yes (multi-device daisy chain)
Supported FPGA Families Altera Cyclone, Cyclone II, Stratix, Stratix GX, Apex series Cyclone, Cyclone II, APEX II, APEX 20K, ACEX 1K, Mercury, Excalibur
Configuration Clock User-programmable internal oscillator Internal / external via DCLK
Programming Cycles 100 minimum endurance cycles —
Programming Voltage 3.3 V in-system (no external VPP) —
Lead-Free / RoHS Lead-free per Altera/Intel Pb-free roadmap —
安裝類型 Surface Mount (PQFP) Surface Mount
MSL 等級 [DATA_NEEDED: MSL rating] —
Product Type — Enhanced Configuration Device (Serial Configuration PROM)
Memory Technology — Flash (in-system programmable)
介面 — Serial FPGA configuration (Altera/Intel proprietary)
Programming Interface — JTAG (IEEE 1149.1) / ISP
Page Reprogram Cycles — 100 minimum
RoHS 狀態 — Unknown
生命週期狀態 — Obsolete (Altera/Intel legacy configuration device)

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