EPC8QC100N vs EPC8QC100C 比較

詳細並排比較 EPC8QC100N 由 Intel 與 EPC8QC100C 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC8QC100N EPC8QC100C
品牌 Intel Altera
類別 Memory ICs Memory ICs
生命週期狀態 Obsolete Obsolete
記憶體類型 Flash (NOR, configuration PROM) Flash-based Configuration PROM
記憶體容量 8 Mbit (8,388,608 bits) 8 Mbit
組織 512K words x 16 bits —
Configuration Device Family EPC8 (Enhanced Configuration Device) —
Supply Voltage (VCC) 3.0 V to 3.6 V (typ. 3.3 V) —
Maximum Configuration Clock 66.7 MHz —
Programmability IEEE Std. 1532 in-system programmable (ISP) —
Programming Interface JTAG (IEEE 1149.1) + Jam STAPL JTAG / Altera ByteBlaster / USB-Blaster
Package Type Plastic Quad Flat Pack (PQFP-100) —
腳位數 100 —
工作溫度 0 C to +70 C (commercial, N suffix) -40C to +85C (industrial)
nINIT_CONF Pin Yes (private JTAG instruction to start FPGA configuration) —
Compatible FPGAs Altera Stratix, Stratix GX, Cyclone, APEX 20K series —
RoHS 狀態 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance status]
MSL 等級 [DATA_NEEDED: Moisture Sensitivity Level] [DATA_NEEDED: MSL rating]
Configuration Schemes — Passive Serial, Concurrent (up to 8 chains), Parallel
Target FPGA Compatibility — Altera APEX, Stratix, Cyclone, ACEX, Mercury, FLEX series
封裝 — 100-Pin PQFP (20x14 mm)
安裝類型 — Surface Mount
Operating Voltage — 3.3 V typical
Configuration Interface — Serial (DCLK/DATA) or Parallel
Max Configuration Clock — [DATA_NEEDED: max DCLK frequency]
Flash Erase/Program Cycles — [DATA_NEEDED: endurance cycles]
Lead-Free — [DATA_NEEDED: lead-free status]

資料表與資源

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