EPF10K130EBC356-1N vs EPF10K100EBC356-1N 比較
詳細並排比較 EPF10K130EBC356-1N 由 Altera 與 EPF10K100EBC356-1N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPF10K130EBC356-1N | EPF10K100EBC356-1N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | FLEX 10KE | FLEX 10KE |
| Typical Gates | 130,000 | 100,000 |
| Maximum System Gates | [DATA_NEEDED: maximum system gates for EPF10K130E] | — |
| Logic Elements (LEs) | 6,656 | — |
| Embedded Array Blocks (EABs) | [DATA_NEEDED: EAB count for EPF10K130E] | — |
| Total RAM Bits | 65,536 | 49,152 |
| User I/O Pins | 274 | 274 |
| 封裝 | 356-LBGA | 356-LBGA (35x35 mm) |
| Package Code | LBGA | — |
| Logic Family | CMOS | CMOS (SRAM-based) |
| Process Technology | 0.22 µm | — |
| Core Supply Voltage | 2.5 V | 2.375 V to 2.625 V (2.5 V nominal) |
| I/O Supply Voltage | 3.3 V | 3.3 V |
| Speed Grade | -1 | — |
| Propagation Delay | 0.6 ns | 0.6 ns |
| Maximum Internal Frequency | 333.33 MHz | — |
| 工作溫度 | 0 °C to 70 °C (Commercial) | 0C to +70C (commercial) |
| JTAG Boundary-Scan | IEEE Std. 1149.1-1990 compliant | — |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 (33/66 MHz, 3.3 V and 5.0 V) | — |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance for EPF10K130EBC356-1N] | Non-RoHS (legacy 'N' suffix) |
| Series | — | FLEX-10KE |
| Logic Elements / Cells | — | 4,992 |
| Logic Array Blocks (LABs) | — | 624 |
| Lead-Free | — | Yes (Pb-free 'N' suffix per Altera legacy scheme) |