EPF10K50GC403-3 vs EPF10K50GC403-4 比較
詳細並排比較 EPF10K50GC403-3 由 Altera 與 EPF10K50GC403-4 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPF10K50GC403-3 | EPF10K50GC403-4 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | FLEX 10K | FLEX 10KA |
| Typical Gate Count | 50,000 gates | — |
| Logic Elements (Cells) | 2,880 | — |
| Maximum Operating Frequency | 125 MHz | — |
| Process Technology | 0.42 µm CMOS | 0.42 µm CMOS SRAM |
| Core Supply Voltage | 5 V | — |
| I/O Supply Voltage | 3.3 V or 5 V (MultiVolt) | — |
| 封裝 | 403-pin CPGA | 403-pin CPGA (Ceramic Pin Grid Array) |
| Speed Grade | -3 | -4 |
| Embedded Array Blocks (EABs) | Yes (per datasheet) | 20 |
| Logic Array Blocks (LABs) | Yes (per datasheet) | — |
| JTAG Boundary Scan | IEEE Std 1149.1 (per family datasheet) | — |
| Configuration Method | SRAM-based, external configuration device required | — |
| 工作溫度 | [DATA_NEEDED: operating temperature grade] | [DATA_NEEDED: operating temperature range] |
| RoHS 狀態 | Compliant (per Kjr Technology listing) | [DATA_NEEDED: RoHS compliance status] |
| Logic Elements | — | 2,880 |
| Typical Gates | — | 50,000 |
| Maximum Internal Clock Frequency | — | 125 MHz |
| 供應電壓 | — | 4.75 V to 5.25 V (5 V nominal) |
| I/O Standards | — | 3.3 V or 5 V configurable (multiVolt) |
| 安裝類型 | — | Through-hole (CPGA) |
| Configuration Memory | — | SRAM (in-system programmable) |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |