EPF10K50RC240-3 vs EPF10K20RC208-3 比較

詳細並排比較 EPF10K50RC240-3 由 Altera 與 EPF10K20RC208-3 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPF10K50RC240-3 EPF10K20RC208-3
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete 啟用中
Series FLEX 10K EPF10K20
Family Flex 10K FLEX 10K
Logic Cells 2,880 —
Usable Gates (typical) 50,000 —
Total Gates (max) 116,000 (per family) —
Logic Array Blocks (LABs) 360 144
Embedded Array Blocks (EABs) 10 (per family) —
User I/Os 189 —
Maximum Internal Frequency 125 MHz —
Propagation Delay 0.6 ns (typical, per family) [DATA_NEEDED: propagation delay in ns]
Supply Voltage (Core) 5 V —
Technology CMOS —
封裝 240-RQFP (RQFP-240 with Exposed Pad) —
安裝類型 Surface Mount Surface Mount
工作溫度 0 C to +70 C (commercial) 0°C to +70°C (Commercial)
Configuration Method JTAG / EPC configuration device —
Programming Tool Support MAX+PLUS II / Quartus (legacy) —
MSL 等級 [DATA_NEEDED: MSL Level] —
RoHS 狀態 [DATA_NEEDED: RoHS Status] Compliant
Lead-Free [DATA_NEEDED: Lead-Free Status] —
Device Type — FPGA (Field Programmable Gate Array)
Typical Gates — 20,000
Logic Elements (Cells) — 1,152
User I/O Pins — 147
Embedded SRAM — 12,288 bits
Maximum Operating Frequency — 125 MHz
Process Technology — 0.42 µm CMOS
Supply Voltage (VCCINT) — 5.0 V
I/O Standard — 5V TTL/CMOS
Package Type — 208-RQFP (Power Quad Flat Pack) with exposed pad
Speed Grade — -3
Configuration Interface — Serial (EPC1/EPC2/EPC16 compatible)
JTAG Support — Yes (IEEE 1149.1 BST)

資料表與資源

瀏覽所有產品 建立 BOM 索取報價