EPF10K70RC240-2N vs EPF10K70RC240-3N 比較

詳細並排比較 EPF10K70RC240-2N 由 Intel 與 EPF10K70RC240-3N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPF10K70RC240-2N EPF10K70RC240-3N
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Series FLEX 10K —
Logic Elements / Cells 3,744 —
Total Gates 70,000 (typical) —
System Gates 118,000 —
Number of LABs 468 —
Embedded Memory (bits) 18,432 —
User I/O Pins 189 —
供應電壓 5 V —
Logic Family CMOS —
Process Technology 0.42 µm 0.42 µm CMOS SRAM
Maximum Operating Frequency 125 MHz —
Propagation Delay 0.4 ns —
Package Type 240-RQFP (BFQFP with exposed pad) —
安裝類型 Surface Mount Surface Mount
工作溫度 0 °C to 70 °C (Commercial) Commercial (0C to +70C)
Configuration Technology SRAM-based (volatile, requires external config ROM) —
Programming Interface JTAG / passive serial —
RoHS 狀態 [DATA_NEEDED: RoHS compliance flag] [DATA_NEEDED: confirm RoHS - FLEX 10K predates RoHS directive]
Family — FLEX 10K
Logic Elements (LEs) — 3,744
Equivalent Gates — 70,000
Embedded Array Blocks (EABs) — [DATA_NEEDED: exact EAB count]
Total RAM Bits — 18,432
User I/Os — 189
Logic Array Blocks (LABs) — 468
封裝 — 240-pin RQFP (BFQFP with exposed pad)
Speed Grade — -3 (0.5 ns typical propagation delay)
Supply Voltage (VCCINT/VCCIO) — 5.0 V
Configuration Method — Passive serial / Passive parallel / JTAG
Maximum Internal Frequency — 125 MHz
I/O Standards Supported — 5.0 V tolerant, 3.3 V, 2.5 V (MultiVolt)
JTAG Support — IEEE 1149.1 boundary-scan compliant
PCI Compliance — PCI SIG Local Bus Specification Revision 2.2
Lead-Free / Pb-Free Finish — Yes (N suffix)

資料表與資源

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