EPF10K70RC240-3N vs EPF10K70RC240-2 比較
詳細並排比較 EPF10K70RC240-3N 由 Intel 與 EPF10K70RC240-2 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPF10K70RC240-3N | EPF10K70RC240-2 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | FLEX 10K | FLEX 10K |
| Logic Elements (LEs) | 3,744 | — |
| Equivalent Gates | 70,000 | — |
| Embedded Array Blocks (EABs) | [DATA_NEEDED: exact EAB count] | 9 |
| Total RAM Bits | 18,432 | — |
| User I/Os | 189 | — |
| Logic Array Blocks (LABs) | 468 | — |
| 封裝 | 240-pin RQFP (BFQFP with exposed pad) | 240-BFQFP Exposed Pad (RQFP, gull-wing) |
| Speed Grade | -3 (0.5 ns typical propagation delay) | -2 |
| Process Technology | 0.42 µm CMOS SRAM | 0.42 µm CMOS |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| 工作溫度 | Commercial (0C to +70C) | 0°C to +70°C (commercial) |
| Configuration Method | Passive serial / Passive parallel / JTAG | — |
| Maximum Internal Frequency | 125 MHz | 125 MHz |
| I/O Standards Supported | 5.0 V tolerant, 3.3 V, 2.5 V (MultiVolt) | — |
| JTAG Support | IEEE 1149.1 boundary-scan compliant | — |
| PCI Compliance | PCI SIG Local Bus Specification Revision 2.2 | — |
| Lead-Free / Pb-Free Finish | Yes (N suffix) | — |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: confirm RoHS - FLEX 10K predates RoHS directive] | unknown |
| Logic Elements / Cells | — | 3,744 |
| Total Gates | — | 70,000 (typical) |
| Number of LABs/CLBs | — | 468 |
| Number of Flip-Flops | — | 18,432 |
| Maximum User I/O | — | 189 |
| Number of I/O Banks | — | [DATA_NEEDED: I/O bank count] |
| 工作電源電壓 | — | 5 V |
| Programmability | — | SRAM-based, in-system programmable |
| Configuration Interface | — | Serial configuration EPROM, JTAG (IEEE 1149.1) |