EPF10K70RC240-4N vs EPF10K70RC240-3N 比較

詳細並排比較 EPF10K70RC240-4N 由 Altera 與 EPF10K70RC240-3N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPF10K70RC240-4N EPF10K70RC240-3N
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family FLEX-10K FLEX 10K
Typical Gates 70,000 —
Logic Elements (LEs) / Cells 3,744 —
Number of LABs/CLBs 468 —
Total RAM Bits 18,432 18,432
User I/O Count 189 —
Number of I/O Banks [DATA_NEEDED: I/O bank count] —
供應電壓 5 V —
Process Technology 0.42 µm CMOS 0.42 µm CMOS SRAM
Operating Frequency (max) 125 MHz —
Propagation Delay ~0.4 ns (per LE, -4 speed grade) —
Configuration Method SRAM (volatile, external PROM required) Passive serial / Passive parallel / JTAG
工作溫度 0 °C to +70 °C (Commercial) Commercial (0C to +70C)
封裝 240-BFQFP Exposed Pad (RQFP-240, Gull-Wing) 240-pin RQFP (BFQFP with exposed pad)
安裝類型 Surface Mount Surface Mount
RoHS 狀態 Compliant (per Altera product page) [DATA_NEEDED: confirm RoHS - FLEX 10K predates RoHS directive]
Logic Elements (LEs) — 3,744
Equivalent Gates — 70,000
Embedded Array Blocks (EABs) — [DATA_NEEDED: exact EAB count]
User I/Os — 189
Logic Array Blocks (LABs) — 468
Speed Grade — -3 (0.5 ns typical propagation delay)
Supply Voltage (VCCINT/VCCIO) — 5.0 V
Maximum Internal Frequency — 125 MHz
I/O Standards Supported — 5.0 V tolerant, 3.3 V, 2.5 V (MultiVolt)
JTAG Support — IEEE 1149.1 boundary-scan compliant
PCI Compliance — PCI SIG Local Bus Specification Revision 2.2
Lead-Free / Pb-Free Finish — Yes (N suffix)

資料表與資源

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