EPF8820ARI208-4H vs EPF8820ARI208-2N 比較

詳細並排比較 EPF8820ARI208-4H 由 Altera 與 EPF8820ARI208-2N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPF8820ARI208-4H EPF8820ARI208-2N
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete NRND
Family FLEX 8000 FLEX 8000
Device Type Loadable PLD / SRAM-based FPGA —
Usable Gates 8,000 8,820
Logic Elements / Cells 672 —
Flip-Flops 820 —
Embedded Array Blocks (EABs) 8 (2 Kbit each) —
Total Inputs 152 (4 dedicated + 148 I/O) —
I/O Lines 148 —
Propagation Delay (tpd) 5.5 ns (speed grade -4) —
Maximum Internal Frequency 125 MHz —
Process Technology 0.42 um CMOS, SRAM-based —
Supply Voltage (VCCINT) 4.5 V to 5.5 V (nominal 5 V) —
I/O Standard Support 3.3 V or 5 V configurable —
封裝 208-pin Plastic Quad Flatpack (RQFP / PQFP), 0.5 mm pitch, gull-wing 208-pin RQFP (Plastic Quad Flat Pack)
Operating Temperature Grade Industrial —
Terminal Form Gull Wing (Surface Mount) —
Package Code FQFP —
Programming Method SRAM (in-system) via JTAG / EPC —
RoHS 狀態 [DATA_NEEDED: rohs status] [DATA_NEEDED: RoHS compliance per specific date code]
Status Obsolete / NRND —
Logic Elements — 504
Maximum User I/O — 78
LABs (Logic Array Blocks) — 63
Logic Elements per LAB — 8
Speed Grade — -2 (mid-tier)
安裝類型 — Surface Mount
Core Supply Voltage — 5.0 V
工作溫度 — 0C to +70C (commercial) / -40C to +85C (industrial)
Programming Technology — SRAM (volatile, requires configuration device)
Boundary Scan — IEEE 1149.1 (JTAG) compliant
Configuration Method — Passive serial / JTAG / Altera EPC configuration device
Lead-Free — Yes (N suffix indicates lead-free assembly)

資料表與資源

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