EPM1270T144C3N vs EPM1270T144C5N 比較
詳細並排比較 EPM1270T144C3N 由 Intel 與 EPM1270T144C5N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM1270T144C3N | EPM1270T144C5N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Device Family | MAX II | — |
| Logic Elements (LEs) | 1270 | 1270 |
| Equivalent Macrocells | 980 | — |
| User Flash Memory (UFM) | 8 Kbits | — |
| Maximum User I/O | 212 | — |
| Operating Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Internal Performance | [DATA_NEEDED: max internal frequency MHz] | — |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: ns by speed grade] | — |
| Speed Grade | C3 (commercial, -3) | -5 |
| 封裝 | 144-pin TQFP (T144) | TQFP-144 (T144), 22 x 22 mm, 0.5 mm pitch |
| 工作溫度 | 0C to +85C (commercial) | 0 °C to +85 °C (Commercial) |
| Configuration Memory | Internal Flash (non-volatile, instant-on) | Internal flash (non-volatile, instant-on) |
| Programming Interface | JTAG (IEEE 1149.1) / IEEE 1532 | JTAG (IEEE 1149.1), In-System Programmable |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | Compliant | Compliant (lead-free) |
| LE Family | MAX II (low-power, non-volatile) | — |
| Family | — | MAX II |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 980 |
| Maximum User I/Os | — | 212 |
| Number of Logic Array Blocks (LABs) | — | 127 |
| Process Technology | — | 0.18 µm |
| Propagation Delay (tPD) | — | 6.2 ns |
| Maximum Internal Frequency | — | 201.1 MHz |
| Supply Voltage (Core) | — | 2.5 V / 3.3 V |
| Supply Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| 無鹵素 | — | Compliant |