EPM1270T144C5N vs EPM1270T144C3N 比較

詳細並排比較 EPM1270T144C5N 由 Altera 與 EPM1270T144C3N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM1270T144C5N EPM1270T144C3N
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Family MAX II —
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 980 —
Logic Elements (LEs) 1270 1270
Maximum User I/Os 212 —
Number of Logic Array Blocks (LABs) 127 —
Process Technology 0.18 µm —
Propagation Delay (tPD) 6.2 ns —
Maximum Internal Frequency 201.1 MHz —
Supply Voltage (Core) 2.5 V / 3.3 V —
Supply Voltage (VCCIO) 1.5 V / 1.8 V / 2.5 V / 3.3 V —
封裝 TQFP-144 (T144), 22 x 22 mm, 0.5 mm pitch 144-pin TQFP (T144)
工作溫度 0 °C to +85 °C (Commercial) 0C to +85C (commercial)
Speed Grade -5 C3 (commercial, -3)
Programming Interface JTAG (IEEE 1149.1), In-System Programmable JTAG (IEEE 1149.1) / IEEE 1532
Configuration Memory Internal flash (non-volatile, instant-on) Internal Flash (non-volatile, instant-on)
RoHS 狀態 Compliant (lead-free) Compliant
無鹵素 Compliant —
安裝類型 Surface Mount Surface Mount
Device Family — MAX II
Equivalent Macrocells — 980
User Flash Memory (UFM) — 8 Kbits
Maximum User I/O — 212
Operating Voltage (VCCINT) — 1.8 V
I/O Voltage (VCCIO) — 1.5 V / 1.8 V / 2.5 V / 3.3 V
Internal Performance — [DATA_NEEDED: max internal frequency MHz]
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: ns by speed grade]
LE Family — MAX II (low-power, non-volatile)

資料表與資源

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