EPM240GT100C3 vs EPM240GT100C3N 比較

詳細並排比較 EPM240GT100C3 由 Intel 與 EPM240GT100C3N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Intel
EPM240GT100C3N EPM240GT100C3N - MAX II CPLD 240 LE TQFP-100 | Intel

EPM240GT100C3N - MAX II CPLD 240 LE TQFP-100 | Intel

EPM240GT100C3N ✓ 啟用中

規格比較

參數 EPM240GT100C3 EPM240GT100C3N
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Family MAX II —
Logic Elements (LE) 240 240
Equivalent Macro Cells 192 —
Pin-to-Pin Delay (tPD) 4.7 ns 4.7 ns
Maximum Internal Frequency (fMAX) 304 MHz —
User I/O Count 80 —
User Flash Memory (UFM) 8 Kbit 8 Kbits
Process Technology 0.18 µm 6-layer-metal flash 0.18 µm 6-layer-metal flash
Core Supply Voltage 1.8 V (internal) —
I/O Bank Voltages (MultiVolt) 1.5 V / 1.8 V / 2.5 V / 3.3 V —
Programming Interface IEEE 1149.1 JTAG (ISP) —
封裝 TQFP-100 (100-TQFP, 16 × 16 mm, 0.5 mm pitch) TQFP-100 (GT100), 16 x 16 mm, 0.5 mm pitch
工作溫度 0 °C to 85 °C (commercial, C3 suffix) 0 °C to +85 °C (commercial, suffix C)
安裝類型 Surface Mount Surface Mount
MSL 等級 3 (168 hours) —
Manufacturer — Intel (formerly Altera)
Series — MAX II
Device Family — MAX II G (instant-on, non-volatile CPLD)
Equivalent Macrocells — 192
User I/O Pins — 80
Core Voltage — 3.3 V
MultiVolt I/O Standards — LVTTL, LVCMOS, PCI, SSTL (1.5 V / 1.8 V / 2.5 V / 3.3 V)
Programmability — In-System Programmable (ISP) via JTAG
Lead-Free / RoHS — Lead Free, RoHS Compliant

資料表與資源

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