EPM240T100C4 vs EPM240T100C5N 比較
詳細並排比較 EPM240T100C4 由 Intel 與 EPM240T100C5N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM240T100C4 | EPM240T100C5N |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Series | MAX II | — |
| Programmable Type | In System Programmable | — |
| Number of Macrocells | 192 | — |
| Number of Logic Elements/Blocks | 240 | — |
| Number of User I/O | 80 | — |
| Maximum Propagation Delay (tPD) | 4.7 ns | — |
| Internal Supply Voltage | 2.5 V / 3.3 V | — |
| I/O Bank Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) | — |
| Process Technology | 0.18 µm CMOS, non-volatile Flash | 0.18 µm, 6-layer-metal flash |
| User Flash Memory | 8 Kbits (typical) | — |
| 封裝 / 外殼 | 100-pin TQFP | — |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | 0 °C to +85 °C (TJ, commercial) | 0 °C to +85 °C (commercial, 'C' suffix) |
| Programming Interface | JTAG (IEEE 1149.1) - ISP | JTAG (IEEE 1149.1) / ISP |
| Supplier Device Package | 100-TQFP (16 × 16 mm, 0.5 mm pitch) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Compliant (lead-free) |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Family | — | MAX II |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements (LEs) | — | 240 |
| Equivalent Macrocells | — | 192 |
| On-Chip User Flash | — | 8 Kbits |
| Maximum User I/O Pins | — | 80 |
| Number of I/O Banks | — | 4 |
| Pin-to-Pin Delay (speed grade 5) | — | 4.7 ns |
| Maximum Internal Frequency | — | 201.1 MHz |
| Core Supply Voltage (VCCINT) | — | 2.5 V / 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| 封裝 | — | 100-pin TQFP (T100), 14x14 mm |