EPM240T100C5N vs EPM240GT100C4 比較

詳細並排比較 EPM240T100C5N 由 Intel 與 EPM240GT100C4 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EPM240GT100C4 EPM240GT100C4 - MAX II CPLD, 240 LE, 100-TQFP | Altera

EPM240GT100C4 - MAX II CPLD, 240 LE, 100-TQFP | Altera

EPM240GT100C4 ✓ 啟用中

規格比較

參數 EPM240T100C5N EPM240GT100C4
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Family MAX II MAX II
Device Type CPLD (Complex Programmable Logic Device) —
Logic Elements (LEs) 240 —
Equivalent Macrocells 192 192
On-Chip User Flash 8 Kbits —
Maximum User I/O Pins 80 —
Number of I/O Banks 4 —
Pin-to-Pin Delay (speed grade 5) 4.7 ns —
Maximum Internal Frequency 201.1 MHz —
Process Technology 0.18 µm, 6-layer-metal flash 0.18-µm, 6-layer-metal flash CMOS
Core Supply Voltage (VCCINT) 2.5 V / 3.3 V —
I/O Supply Voltage (VCCIO) 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) —
Programming Interface JTAG (IEEE 1149.1) / ISP JTAG (IEEE 1149.1) / In-System Programmable (ISP)
工作溫度 0 °C to +85 °C (commercial, 'C' suffix) —
封裝 100-pin TQFP (T100), 14x14 mm 100-TQFP (TQFP-100), 16 x 16 mm, 0.5 mm pitch
安裝類型 Surface Mount Surface Mount (Gull-Wing leads)
RoHS 狀態 Compliant (lead-free) —
Logic Elements (LE) — 240
Pin-to-Pin Delay (tPD) — 4.7 ns
Propagation Delay — 6.1 ns (max)
User I/O Pins (max) — 80
On-chip Flash Memory (UFM) — 8 Kbits
I/O Standards Supported — 1.5 V, 1.8 V, 2.5 V, 3.3 V (MultiVolt)
工作溫度範圍 — 0°C to +85°C (Commercial)
Supply Voltage (Core) — 3.3 V
Lead-Free / RoHS — Lead-Free (per FindIC entry); RoHS compliance [DATA_NEEDED: verify against manufacturer datasheet]

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