EPM240T100I3N vs EPM240T100A5N 比較
詳細並排比較 EPM240T100I3N 由 Intel 與 EPM240T100A5N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EPM240T100I3N - 192-Macrocell MAX II CPLD, 100-TQFP, Industrial | Intel
EPM240T100I3N ⚠ 最後購買機會規格比較
| 參數 | EPM240T100I3N | EPM240T100A5N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | 啟用中 |
| Family | MAX II | MAX II |
| Device Logic Elements / Macrocells | 192 macrocells | — |
| Maximum User I/O Pins | 80 | — |
| Number of Logic Array Blocks (LABs) | 4 | — |
| On-chip User Flash Memory | 8 Kbits | — |
| Internal Performance | 304 MHz | — |
| Pin-to-pin Logic Delay (tPD1) | 4.6 ns | — |
| Global Clock Networks | 4 | — |
| Technology Node | 0.18 um, 6-layer-metal flash CMOS | — |
| Supply Voltage - Core | 2.5 V / 3.3 V | — |
| MultiVolt I/O Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| 工作接面溫度 | -40C to +100C (industrial, 'I' grade) | — |
| Speed Grade | 3 | — |
| 封裝 | TQFP-100 (T100), 14x14 mm, 0.5 mm pitch | 100-pin TQFP (14 x 14 x 1.0 mm) |
| Programming Interface | JTAG / IEEE 1149.1 ISP | JTAG (IEEE 1149.1) / ISP |
| Instant-on (non-volatile) | Yes (flash-based) | — |
| MSL 等級 | 3 (per JEDEC J-STD-020) | — |
| RoHS 狀態 | Compliant | Compliant (Pb-free) |
| Macro Cells | — | 192 |
| Logic Elements (LE) | — | 240 |
| User I/O Count | — | 80 |
| Pin-to-Pin Logic Delay (tPD) | — | 4.7 ns |
| Maximum Internal Frequency | — | 201.1 MHz |
| 供應電壓 | — | 2.5 V / 3.3 V |
| I/O Bank Count | — | 4 (multi-voltage) |
| Process Technology | — | 0.18 µm |
| Configuration Memory | — | On-chip Flash (instant-on) |
| 工作溫度 | — | 0C to +85C (commercial, "A5N" suffix) |
| 安裝類型 | — | Surface Mount |