EPM3032ALC44-10N vs EPM3064ALC44-7N 比較
詳細並排比較 EPM3032ALC44-10N 由 Altera 與 EPM3064ALC44-7N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EPM3064ALC44-7N - 64-Macrocell MAX 3000A CPLD, 7.5ns, 44-PLCC | Intel / Altera
EPM3064ALC44-7N ⚠ 最後購買機會規格比較
| 參數 | EPM3032ALC44-10N | EPM3064ALC44-7N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | 最後購買 |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Gates | 600 gates | — |
| Macrocells | 32 | 64 |
| Logic Array Blocks (LABs) | 2 | 2 |
| User I/O Pins | 34 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Internal fMAX | 103.1 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) | — |
| Technology | CMOS EEPROM-based | — |
| In-System Programmability | Yes, via IEEE 1149.1 JTAG | Yes (IEEE Std 1149.1 JTAG) |
| ISP Standard Compliance | IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | Yes, IEEE 1149.1 compliant | — |
| 封裝 | 44-pin PLCC (J-Lead, surface mount) | 44-pin PLCC |
| 安裝類型 | Surface Mount | Surface Mount (PLCC socket compatible) |
| 工作溫度 | [DATA_NEEDED: industrial/commercial range] | 0C to +70C (commercial) |
| RoHS 狀態 | [DATA_NEEDED: compliant or non-compliant] | [DATA_NEEDED: RoHS status] |
| Logic IC Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 1,250 |
| Number of User I/O Pins | — | 34 |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Maximum Frequency | — | 135.1 MHz |
| Core Technology | — | CMOS EEPROM |
| I/O Tolerance | — | 5 V-tolerant |
| Programming Software | — | Quartus II / Quartus Prime (legacy MAX+PLUS II supported) |