EPM3032ALC44-4 vs EPM3032ALC44-7 比較
詳細並排比較 EPM3032ALC44-4 由 Altera 與 EPM3032ALC44-7 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM3032ALC44-4 | EPM3032ALC44-7 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 32 | — |
| Logic Array Blocks (LABs) | 2 | 2 |
| User I/O Pins | 34 | — |
| Pin-to-Pin Delay (tPD) | 4.5 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V (MultiVolt: 5.0 V / 3.3 V / 2.5 V compatible) | — |
| Usable Gates | 600 to 10,000 (MAX 3000A family range) | — |
| 封裝 | 44-pin PLCC (J-Lead) | 44-pin PLCC (J-Lead), 16.59 x 16.59 mm, 3.81 mm height |
| 工作溫度 | 0°C to +70°C (Commercial) | 0 °C to +70 °C (Commercial) |
| Technology | CMOS EEPROM-based | — |
| In-System Programmability (ISP) | Yes, IEEE Std. 1532 compliant | — |
| Boundary-Scan Test | IEEE Std. 1149.1 (JTAG) | — |
| Programming Interface | JTAG (ByteBlaster / MasterBlaster) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Not Compliant (per Arrow listing) |
| 安裝類型 | Surface Mount (PLCC J-Lead) | Surface Mount |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements / Macrocells | — | 32 macrocells |
| System Gates | — | 600 |
| Number of User I/O Pins | — | 34 |
| Global Clocks | — | 2 |
| Propagation Delay (tPD1, max) | — | 7.5 ns |
| Maximum Internal Frequency (fMAX) | — | 138.9 MHz |
| Supply Voltage (VCCINT / VCCIO) | — | 3.3 V |
| I/O Tolerant Voltage | — | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| Program Memory Type | — | EEPROM |
| In-System Programming (ISP) | — | Yes - IEEE 1149.1 JTAG |
| Part Status | — | Obsolete |
| ECCN | — | EAR99 |