EPM3064ALC44-10N vs EPM3064ALC44-4 比較
詳細並排比較 EPM3064ALC44-10N 由 Altera 與 EPM3064ALC44-4 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM3064ALC44-10N - MAX 3000A CPLD, 64 Macrocells, 34 I/O | Intel / Altera
EPM3064ALC44-10N Obsolete規格比較
| 參數 | EPM3064ALC44-10N | EPM3064ALC44-4 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Family | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | 2 |
| User I/O Pins | 34 | 34 |
| Usable Gates | 1,250 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V | — |
| I/O Bank Voltage (VCCIO) | 3.0 V to 3.6 V (MultiVolt) | — |
| Configuration Memory | CMOS EEPROM | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, IEEE 1532 compliant) | Yes (IEEE 1149.1 JTAG, 3.3-V ISP) |
| 封裝 | 44-pin PLCC (LC44) | — |
| 安裝類型 | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC J-Lead, socket-compatible) |
| 工作溫度 | [DATA_NEEDED: commercial / industrial grade] | — |
| RoHS 狀態 | Compliant | [DATA_NEEDED: rohs status] |
| Open-Drain Output Option | Yes (per I/O pin) | — |
| Output Slew-Rate Control | Programmable | — |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |
| Part Family | — | MAX 3000A |
| Pin-to-Pin Delay (tPD) | — | 4.5 ns |
| Propagation Delay | — | 4.5 ns (max) |
| Supply Voltage - Internal (VCCINT) | — | 3.3 V |
| Supply Voltage - I/O (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V |
| Program Memory Type | — | EEPROM (non-volatile) |
| 封裝 / 外殼 | — | 44-LCC (J-Lead), PLCC-44 |
| Operating Temperature Grade | — | Commercial |
| Terminal Form | — | J BEND |
| Package Code | — | QCCJ (J-Lead Chip Carrier) |
| Package Shape | — | Square |
| Number of Terminals | — | 44 |
| Technology | — | CMOS EEPROM |