EPM3064ALC44-10N vs EPM3064ALC44-7N 比較
詳細並排比較 EPM3064ALC44-10N 由 Altera 與 EPM3064ALC44-7N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM3064ALC44-10N - MAX 3000A CPLD, 64 Macrocells, 34 I/O | Intel / Altera
EPM3064ALC44-10N ObsoleteIntel
EPM3064ALC44-7N - 64-Macrocell MAX 3000A CPLD, 7.5ns, 44-PLCC | Intel / Altera
EPM3064ALC44-7N ⚠ 最後購買機會規格比較
| 參數 | EPM3064ALC44-10N | EPM3064ALC44-7N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Product Family | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | 2 |
| User I/O Pins | 34 | — |
| Usable Gates | 1,250 | 1,250 |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V | 3.3 V |
| I/O Bank Voltage (VCCIO) | 3.0 V to 3.6 V (MultiVolt) | — |
| Configuration Memory | CMOS EEPROM | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, IEEE 1532 compliant) | Yes (IEEE Std 1149.1 JTAG) |
| 封裝 | 44-pin PLCC (LC44) | 44-pin PLCC |
| 安裝類型 | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| 工作溫度 | [DATA_NEEDED: commercial / industrial grade] | 0C to +70C (commercial) |
| RoHS 狀態 | Compliant | [DATA_NEEDED: RoHS status] |
| Open-Drain Output Option | Yes (per I/O pin) | — |
| Output Slew-Rate Control | Programmable | — |
| Family | — | MAX 3000A |
| Logic IC Type | — | CPLD (Complex Programmable Logic Device) |
| Number of User I/O Pins | — | 34 |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Maximum Frequency | — | 135.1 MHz |
| Core Technology | — | CMOS EEPROM |
| I/O Tolerance | — | 5 V-tolerant |
| Programming Software | — | Quartus II / Quartus Prime (legacy MAX+PLUS II supported) |