EPM3064ATC100-4 vs EPM3064ATC100-10N 比較
詳細並排比較 EPM3064ATC100-4 由 Altera 與 EPM3064ATC100-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM3064ATC100-4 | EPM3064ATC100-10N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | 啟用中 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (EEPROM-based) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 64 | — |
| Logic Array Blocks (LABs) | 2 | 2 |
| Usable Gates | 1,250 (range 600 to 10,000 across family) | 1,250 |
| Maximum User I/O Pins | 34 | 66 |
| Pin-to-Pin Delay (tPD) | 4.5 ns | 10 ns |
| Counter Frequency (fCNT) | 227.3 MHz | — |
| Internal Performance | 222.2 MHz | — |
| Supply Voltage VCCINT | 3.3 V | — |
| I/O Voltage (MultiVolt) | 2.5 V / 3.3 V / 5.0 V | — |
| In-System Programming | Yes (IEEE 1149.1 JTAG) | — |
| Process Technology | CMOS EEPROM | — |
| 封裝 | 100-pin TQFP | 100-pin TQFP |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | 0C to +70C (commercial) [DATA_NEEDED: industrial temp grade option] | 0C to +70C (commercial) |
| RoHS 狀態 | unknown | Compliant (lead-free) |
| Architecture | 5-level Altera MAX | — |
| Macrocells | — | 64 |
| Supply Voltage (VCCINT) | — | 3.3 V (3.0 V to 3.6 V) |
| In-System Programmability | — | Yes - IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Yes - JTAG compliant |
| Configuration Memory | — | Non-volatile EEPROM |
| Program/Erase Cycles | — | 100 minimum |
| MultiVolt I/O | — | Yes - 1.8 V / 2.5 V / 3.3 V / 5 V tolerant |