EPM3064ATC44-10N vs EPM3032ATC44-10N 比較

詳細並排比較 EPM3064ATC44-10N 由 Altera 與 EPM3032ATC44-10N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EPM3064ATC44-10N EPM3064ATC44-10N - 64-Macro Cell MAX 3000A CPLD | Altera

EPM3064ATC44-10N - 64-Macro Cell MAX 3000A CPLD | Altera

EPM3064ATC44-10N ✓ 啟用中

規格比較

參數 EPM3064ATC44-10N EPM3032ATC44-10N
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 Obsolete
Family MAX 3000A —
Device Type CPLD (Complex Programmable Logic Device) —
Usable Gates 1250 600
Macro Cells 64 —
User I/O Pins 34 34
Logic Array Blocks (LABs) 4 2
Pin-to-Pin Delay (tPD) 10 ns —
Maximum Counter Frequency 192.3 MHz —
Supply Voltage (VCCINT) 3.3 V —
I/O Standard MultiVolt (mixed 1.5 V / 1.8 V / 2.5 V / 3.3 V) —
Configuration Memory EEPROM (non-volatile) EEPROM (non-volatile, instant-on)
In-System Programming IEEE Std. 1532 compliant —
Boundary-Scan Test IEEE Std. 1149.1 (JTAG) compliant —
封裝 TQFP-44 (10x10 mm) 44-pin TQFP
安裝類型 Surface Mount Surface Mount
工作溫度 0C to +70C (commercial) —
RoHS 狀態 Compliant Compliant (lead-free)
Pin-Locking Yes (across design iterations) —
Series — MAX 3000A
Device Family — CPLD - Complex Programmable Logic Device
Macrocells — 32
Pin-to-Pin Logic Delay (tPD) — 10 ns
Maximum Counter Frequency (fCNT) — 138.9 MHz
Core Supply Voltage (VCCINT) — 3.3 V
I/O Logic Level Support — 5.0 V / 3.3 V / 2.5 V (MultiVolt)
In-System Programmability — Yes, IEEE 1149.1 JTAG
ISP Standard Compliance — IEEE Std. 1532
Open-Drain I/O Option — Yes, per pin
Operating Temperature (Commercial) — 0 C to +70 C

資料表與資源

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